Input circuits using CMOS transistors are well-known in the art. Typically, they comprise a plurality of inverters, using CMOS transistors, connected in series. An input signal is supplied to the input of a first inverter. The output signal of the first inverter is supplied as the input signal to a second inverter. The output signal of the second inverter is supplied as the input signal of a third inverter and so forth. The output signal from the input circuit is supplied to an electronic circuit performing a desired function. The plurality of serially connected inverters provides for a buffer or acts to reduce noise signals from being introduced into the electronic circuit. Thus, with a plurality of inverters separating the input signal from the electronic circuit, the electronic circuit is immune to noise and the like. Examples of input circuits from the prior art can be found in U.S. Pat. Nos. 4,210,829; 4,296,340; 3,774,053 and 3,603,813.
Though CMOS circuits inherently consume less power than NMOS or Bipolar circuits, a large transient current occurs when the CMOS circuits are switching states. The magnitude of this switch noise becomes a problem as more advanced CMOS processes allow even faster switching speed and more circuits are integrated into one chip, with many large output buffers switching simultaneously. The large transient current will perturb the on-chip power and ground levels. This perturbation may cause the CMOS input circuit to switch erroneously or to slow down dramatically.